Commercially available routers used in data networks are typically comprised of an interface layer defining a plurality of Input/Output (I/O) controllers implementing respective I/O ports, a switching layer that establishes signal pathways between the I/O ports, and a routing layer. The routing layer is responsible for communicating with other routers in the data network. Such peering communication sessions are conducted according to a routing protocol, and their purpose is to exchange route information.
The routing layer is implemented in software executed by a computing entity. The computing entity includes a Central Processing Unit (CPU) and a data storage medium that holds the program instructions executed by the CPU to implement the routing layer functionality.
An increase of the capacity of the routing layer, in terms of augmenting the number of simultaneous peering sessions that can be established, faster processing of the route information, etc., can be effected by increasing the speed of the CPU and providing a larger data storage medium. However, this approach provides a limited solution only and from a practical perspective can yield modest capacity increases at best. Therefore, there is a clear need in the industry to develop novel architectures for a router that are highly scalable.